Fast Timing Analysis for Hardware-Software Co-Synthesis

At the current time, an iterative approach seems to be be -rt suited for iwrdwardsojlware partitioning in hardware/sofhuare CO-synthesis with time constraints. To check the timing constraints the iteration loop contains a timing analysis. Only computation time intensive KT-level simulation provides suflcient timing precision fiir complex processor architectures. We present il hardwure/sofrware timing analysis, which comes c l o s ~ to the precision of an RT-level simulation in a fraction of the computation time and, thus. removes a bottleneck from iterative hardwardsofnuare co-synrhesis. We present rorne results for our co-synthesis system COSYMA.